SN74HC164N

These 8-bit shift registers feature AND-gated serial
1? Wide Operating Voltage Range of 2 V to 6 V
inputs and an asynchronous clear (CLR) input. The
? Outputs Can Drive Up to 10 LSTTL Loads gated serial (A and B) inputs permit complete control
? Low Power Consumption, 80-?A Maximum ICC over incoming data; a low at either input inhibits entry
? Typical tpd = 20 ns of the new data and resets the first flip-flop to the low
level at the next clock (CLK) pulse. A high-level input
? ?4-mA Output Drive at 5 V
enables the other input, which then determines the
? Low Input Current of 1-?A Maximum state of the first flip-flop. Data at the serial inputs can
? AND-Gated (Enable/Disable) Serial Inputs be changed while CLK is high or low, provided the
minimum set-up time requirements are met. Clocking ? Fully Buffered Clock and Serial Inputs
occurs on the low-to-high-level transition of CLK.