AM26C31 Differential Line Receiver (SOIC)

The device features an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The high-performance, low cost CP21xx USB to UART bridge family offers a complete plug and play interface solution that includes royalty-free driver suites and a comprehensive design ecosystem that enables customers to speed time-to-market. Crystal-less operation, in-system programming memory and small body size packages reduce cost, simplify design and shorten development time. The CP2102 is a highly-integrated?USB-to-UART Bridge Controller?providing a simple solution for updating RS-232 designs to USB using a minimum of components and PCB space. The?CP2102?includes a?USB 2.0 full speed function controller, USB transceiver, oscillator, EEPROM or EPROM, and asynchronous serial data bus (UART) with full modem control signals in a compact 5 x 5 mm QFN-28 package.

MAX232 is a communication IC. It is used to convert TTL Signals to RS232 Signal and vice versa.?MAX232?provides RS-232 voltage level outputs (approx. ? 7.5 V) from a single 5 V supply via on-chip charge pumps and external capacitors. This makes it useful for implementing RS-232 in devices that otherwise do not need any voltages outside the 0 V to 5 V range, as power supply design does not need to be made more complicated just for driving the RS-232 in this case.

The receivers reduce RS-232 inputs (which may be as high as ? 25 V), to standard 5 V TTL levels. These receivers have a typical threshold of 1.3 V, and a typical hysteresis of 0.5 V.

The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the band split filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.