Showing 3265–3276 of 3920 results

SFH615A-3

56.00
The SFH615A feature a variety of transfer ratios, low coupling capacitance and high isolation voltage. These couplers have a GaAs infrared diode emitter, which is optically coupled to a silicon planar phototransistor detector, and is incorporated in a plastic DIP-4 package. The coupling devices are designed for signal transmission between two electrically separated circuits. The couplers are end-stackable with 2.54 mm lead spacing. Creepage and clearance distances of > 8 mm are achieved with option 6. This version complies with IEC 60950 (DIN VDE 0805) for reinforced insulation up to an operation voltage of 400 VRMS or DC. Specifications subject to change.

SG3524 Regulating Pulse Width Modulator IC DIP-16 Package

21.00
SG3524 incorporate all the functions required in the construction of a regulating power supply, inverter, or switching regulator on a single chip. It can be used as the control element for high-power-output applications.SG3524 was designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless voltage doublers, and polarity-converter applications employing fixed-frequency, pulse-width modulation (PWM) techniques.

SG3525 Pulse Width Modulation Controller IC DIP-16 Package

42.00
The SG3525A pulse width modulator control circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies.

SGTL5000XNLA3

349.00
Features of SGTL5000XNLA3 Analog inputs ? Stereo LINEIN - External analogue input support ? Stereo LINEIN - Low power codec bypass ? MIC bias was offered ? Adjustable MIC gain ? ADC: -73 dB THD+N (VDDA = 1.8 V) and 85 dB SNR (-60 dB input).   Analog outputs ? Cap less design for HP output ? HP Output: 62.5 mW peak, sine wave @ 1.02 kHz, 16-ohm load at 3.3 V ? HP Output: -80 dB THD+N (VDDA = 1.8 V, 16 load, DAC to headphone) and 100 dB SNR (-60 dB input). ? LINEOUT: -85 dB THD+N (VDDIO = 3.3 V) and 100 dB SNR (-60 dB input).   I/O in digital form of SGTL5000XNLA3 ? I2S port for Application Processor Integrated Digital Processing route ? Graphic equaliser clocking/control, NXP surround, NXP bass, and tone control ? PLL provides for the input of system clocks ranging from 8.0 MHz to 27 MHz; standard audio clocks are derived from PLL.   Power Sources of SGTL5000XNLA3 ? Created to function between 1.62 and 3.6 volts