PIC16F677-I/P PIC Microcontroller, 8051

The PIC12F675 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The data memory is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. The register file is organized as 64 x 8 in the PIC12F675 device. Each register is accessed, either directly or indirectly, through the File Select Register FSR. There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin.

The PIC16C622 device has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. PIC16C622 micro controllers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit micro controllers in their class.