DS90UB913ATRTV-Q1
₹620.00
Features of DS90UB913A
? Automotive applications approved for use with AEC-Q100
– Device temperature grade 2: operating temperature range of -40?C to +105?C
? Support for input pixel clocks between 25 and 100 MHz
? Programmable data payloads include 10-bit and 12-bit payloads with a maximum speed of 100 MHz and 75 MHz, respectively.
? 400 kHz I2C-compatible continuous low latency bidirectional control interface channel
? An embedded clock that supports AC-coupled interconnects by using DC-balanced coding.
? Capable of driving up to 20m of shielded twisted-pair cables or 15m of coaxial cable.
? Power-Over-Coaxial (PoC) functioning that is reliable
? 4 Specific general-purpose input/output devices
? Compatible parallel inputs on serializer?at 1.8, 2.8, or 3.3 volts
? A single 1.8 V power supply
? Compliant with ISO 10605 and IEC 61000-4-2 ESD
? Tiny (5 mm by 5 mm) serializer footprint
Applications? of DS90UB913A
? Automotive
? Surround View Systems (SVS)
? Front Cameras (FC)
? Rear View Cameras (RVC)
? Sensor fusion
? Driver Monitor Cameras (DMS)
? Remote satellite RADAR, ToF, and LIDAR sensors
? Security and surveillance
? Machine vision applications
1500 in stock
Description of DS90UB913A
For data transfer over a single coaxial cable or differential pair, the DS90UB913A-Q1 device features an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel.
Differential signalling is used by the DS90UB913A-Q1 device on the high-speed forward channel and bidirectional control channel data lines. The imagers and video processors in an ECU are the target audience for the serializer and de-serializer combination (Electronic Control Unit).
With two synchronisation signals, a bidirectional control channel bus, and up to 12-bit pixel depth, this device is perfectly suited for driving video data.
Transparent full-duplex communication via a single differential pair conveying asymmetrical-bidirectional control channel data is possible when using TI’s integrated clock technology.
Through the elimination of skew issues between parallel data and clock pathways, this single serial stream makes it easier to carry a large data bus through PCB traces and wire.
By constricting data routes, which in turn reduce PCB layers, cable width, connection size, and connector pins, this drastically lowers system cost. Support for AC-coupled interconnects is provided by internal DC-balanced encoding/decoding.
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