24LC256-I/SN

The 24AA512/24LC512/24FC512 (24XX512*) from Microchip Technology Inc. is a 64K x 8 (512 Kbit) Serial Electrically Erasable PROM that can operate over a wide voltage range (1.7V to 5.5V). It was created for cutting-edge, low-power applications including data collection and personal communications. Additionally, this device has a page write capacity of up to 128 bytes of information. Both random and sequential readings up to the 512K barrier are supported by this device. Up to eight devices can share a bus with functional address lines, providing a maximum address space of 4 Mbit. The common 8-pin plastic DIP, SOIJ, SOIC, TSSOP, DFN, and 14-lead TSSOP packaging are also available for this component. The 8-lead Chip Scale package is another option for the 24AA512. Features: ? A single supply that operates 24AA512 and 24FC512 devices at 1.7V and 24LC512 devices at 2.5V. ? CMOS Low-Power Technology: - A average active current of 400 uA - Typical standby current is 100 nA ? Compatible with 2-Wire Serial Interface and I2CTM ? Up to eight devices can be cascaded ? Noise-cancelling Schmitt Trigger Inputs ? Ground Bounce is eliminated through output slope control. ? Compatibility of 100 kHz and 400 kHz clocks ? Maximum Page Write Time 5 ms. ? Timed Erase/Write Cycle on Your Own ? Page Write Buffer of 128 bytes Equipment Write-Protect ? >4000V ESD Protection ? Over 1,000,000 Erase/Write Cycles ? 200 years of data retention ? The following packages are available: 8-lead PDIP, SOIJ, SOIC, BTSSOP, DFN, Chip Scale, and 14-lead TSSOP. ? RoHS and Pb-Free Compliant ? Ranges of temperatures Industrial (I): -40?F to 85?F Vehicle (E): -40 to 125C

The SST89E5xxRD2 and SST89V5xxRD2 are FlashFlex51 family 8-bit microcontroller devices designed and manufactured using SST's unique and proprietary Super Flash CMOS semiconductor manufacturing technology. SST's clients gain significantly from the split-gate device structure and thick-oxide tunnelling injector in terms of cost and reliability. The devices are pin-for-pin compatible with ordinary 8051 microcontroller devices and use the 8051 instruction set. The devices include 16/24/40/72 K Byte of on-chip flash EEPROM programme memory that is divided into two separate programme memory blocks. The primary Block 0 has 8/16/32/64K Bytes of internal programme memory space, whereas the secondary Block 1 has 8K Bytes of internal programme memory space. The 8-KByte secondary block can be identified to the minimum address point in the 8/16/32/64 K Byte address space, as well as concealed from the programme counter and utilised as an independent EEPROM-like data store. In addition to the on-chip EEPROM programme memory of 16/24/40/72 K Bytes, the devices may address up to 64 K Bytes of external programme memory. In addition to 1024 x 8 bits of on-chip RAM, external RAM of up to 64 K Bytes may be addressed.

The AT24C512C functions as a slave device and communicates with a host controller, also known as the bus master, using a straightforward two-wire digital serial interface that is I2C-compatible. On a serial bus, the master initiates and manages all read and write operations to slave devices, and both the master and slave devices are capable of sending and receiving data. Just two signal lines?Serial Clock (SCL) and Serial Data?make up the serial interface (SDA). The bilateral SDA pin is used to receive command and detailed empirical from the master as well as to transmit data back to the master, while the SCL pin is used to accept the clock signal from the master. To reduce the impact of input spikes and bus noise, the SCL and SDA pins each include Schmitt Triggers and inbuilt spike suppression filters. The Most Significant bit (MSb) is always transmitted first when sending commands or data. After eight bits (one byte) of information have been exchanged during bus communication, the receiving device must answer with an Acknowledge (ACK) or No-Acknowledge (NACK) response bit during such a ninth clock cycle (ack/nack clock cycle) produced by the master. As a result, nine clock cycles are needed to send one byte of data. There must be no gaps or interruptions throughout any data transfer operation since there are no spare clock cycles. AT24C512C-SSHD Datasheet 

The Serial Electrically-Erasable Programmable Read-Only Memory (EEPROM) on the Atmel? AT25320B/640B has 32,768-/65,536-bits and is divided into 4,096/8,192 words with 8 bits each. The device is prepared for usage in a wide range of industrial and commercial settings where moderate and low-voltage functioning are critical requirements. The 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, and 8-ball VFBGA packages for the AT25320B/640B are available in compact sizes. A 3-wire interface made up of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock is used to access and enable the AT25320B/640B. (SCK). No further erase cycle is necessary before Write since every programming cycle is fully self-timed. Programming one of the four blocks of write security into the status register activates block write protection. For added data security, separate instructions for programme enable and programme disable are given. The WP pin offers hardware data protection to guard against unintentional write attempts to the status register. Any serial communication can be halted using the HOLD pin without having to restart the serial sequence.