SN74ALS35AN
The SN74ALS35A contains six independent
noninverters with open-collector outputs. They
perform the Boolean function Y = A. The
open-collector outputs require pullup resistors to
perform correctly. These outputs may be
connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
The SN74ALS35A is characterized for operation
from 0?C to 70?C.
SN74ALS521N
These identity comparators perform comparisons
on two 8-bit binary or BCD words. The
SN74ALS518 provides P = Q outputs, while the
?ALS520 and SN74ALS521 provide P = Q
outputs. The SN74ALS518 has an open-collector
output. The SN74ALS518 and ?ALS520 feature
20-k? pullup resistors on the Q inputs for analog
or switch data.
The SN54ALS520 is characterized for operation
over the full military temperature range of ?55?C
to 125?C. The SN74ALS518, SN74ALS520, and
SN74ALS521 are characterized for operation
from 0?C to 70?C
SN74ALS569AN
The SN74ALS568A decade counter and
?ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). Asynchronous (direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
SN74ALS576BN
scription
These octal D-type edge-triggered flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
These flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
The output-enable (OE) input does not affect
internal operations of the flip-flops. Old data can
be retained or new data can be entered while the
outputs are disabled
SN74F08D
SN74F11N
SN74F174AD
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a
direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred
to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level
and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either
the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0?C to 70?C.
SN74F573DW
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ?F573 are transparent
D-type latches. While the latch enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When the latch enable is taken low, the Q outputs
are latched at the logic levels set up at the D
inputs.
