The 74LS13 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

The 74LS147 TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ?147 and ?LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.

The 74LS189 is a high speed 64-bit RAM organized as a 16- word by 4-bit array. Address inputs are buffered to minimize loading and are fully decoded on-chip. The outputs are 3-state and are in the high impedance state whenever the Chip Select (CS) input is HIGH.