PIC18F2620 Microcontroller

The PIC18F4550 is a 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology. The following are the features:- • High-Current Sink/Source: 25 mA/25 mA • Three External Interrupts • Four Timer modules (Timer0 to Timer3) • Up to 2 Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution 5.2 ns (TCY/16) - Compare is 16-bit, max. resolution 83.3 ns (TCY) - PWM output: PWM resolution is 1 to 10-bit • Enhanced Capture/Compare/PWM (ECCP) module: - Multiple output modes - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart • Enhanced USART module: LIN bus support • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes • 10-Bit, Up to 13-Channel Analog-to-Digital Converter (A/D) module with Programmable Acquisition Time • Dual Analog Comparators with Input Multiplexing

The PIC16F873, PIC16F874, PIC16F876 and PIC16F877 are the four covered devices. Devices for the PIC16F876/873 and PIC16F877/874 available in 28-pin and 40-pin packages, respectively. On 28-pin devices, the Parallel Slave Port is not implemented. Each PIC16F87X device has the ability to access an 8K word block of program memory continuously. Only 11 bits of address are provided by the CALL and GOTO instructions, allowing branching inside any 2K program memory page. PCLATH4:3> provides the upper 2 bits of the address when performing a CALL or GOTO instruction. The user must make sure that the page choose bits are set when performing a CALL or GOTO instruction in order for the chosen programme memory page to be addressed. The full 13-bit PC is popped off the stack whenever a return from a CALL instruction (or interrupt) is performed. Therefore, the return instructions do not need the modification of the PCLATH4:3> bits (which POPs the address from the stack). Data Memory Organization The General Purpose Registers and Special Function Registers are divided up into several banks in the data memory. The bank select bits are bits RP1 (Status:6) and RP0 (Status:5). Each bank stretches to 7Fh (128 bytes). The Special Function Registers are only permitted in the bottom positions of each bank. General Purpose Registers, which are implemented as static RAM, are located above the Special Function Registers. Special Function Registers are present in all installed banks. For code reduction and faster access, some commonly used Special Function Registers from one bank may be duplicated in another bank.