The 74LS73 device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs.
Features:-
? Two Independent Negative Edge Triggered JK Flip-Flops
? Clear Input Resets the Output
? Fast Switching Times
? Operating Temperature up to 70?C
? Standard TTL Switching Voltages
Specifications:-
Parameter Specification
Supply Voltage (VCC) 7 V
Input Voltage (VI) 7 V
Operating free-air temperature range 0?C to +70?C
Storage temperature range ?65?C to +150?C
Related Document:-
74LS73 IC Datasheet
* Product Images are shown for illustrative purposes only and may differ from actual product.
74LS73 Dual JK Flip-Flop with Clear IC (7473 IC) DIP-14 Package
₹61.00
The 74LS73 device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
SKU:
CM74-0060
Category: 74 Series IC
Description
Shipping & Delivery
MAECENAS IACULIS
Vestibulum curae torquent diam diam commodo parturient penatibus nunc dui adipiscing convallis bulum parturient suspendisse parturient a.Parturient in parturient scelerisque nibh lectus quam a natoque adipiscing a vestibulum hendrerit et pharetra fames nunc natoque dui.
ADIPISCING CONVALLIS BULUM
- Vestibulum penatibus nunc dui adipiscing convallis bulum parturient suspendisse.
- Abitur parturient praesent lectus quam a natoque adipiscing a vestibulum hendre.
- Diam parturient dictumst parturient scelerisque nibh lectus.
Scelerisque adipiscing bibendum sem vestibulum et in a a a purus lectus faucibus lobortis tincidunt purus lectus nisl class eros.Condimentum a et ullamcorper dictumst mus et tristique elementum nam inceptos hac parturient scelerisqueĀ vestibulum amet elit ut volutpat.
Related products
74HC04 Hex Inverter IC (7404 IC) DIP-14 Package
₹15.00
74HC138 3-to-8 line Decoder/Demultiplexer IC (74138 IC) DIP-16 Package
₹17.00
74HC157 Quad 2-Input Multiplexer IC (74157 IC) DIP-16 Package
₹20.00
74HC221 Dual Monostable Multivibrator with Reset IC (74221 IC) DIP-16 Package
₹17.00
74HC86 Quad 2-Input EXOR Gate IC (7486 IC) DIP-14 Package
₹14.00
74LS125 Quad Tri-state Buffer IC (74125 IC) DIP-14 Package
₹18.00
This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors.
74LS13 Schmitt Trigger IC (7413 IC) DIP-14 Package
₹35.00
74LS147 Decimal to BCD Priority Encoder IC (74147 IC) DIP-16 Package
₹53.00
The 74LS147 TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ?147 and ?LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.