SN74ALS09N
These devices contain four independent 2-input
positive-AND gates. They perform the Boolean
functions Y = A ? B or Y = A B in positive logic.
The open-collector outputs require pullup
resistors to perform correctly. These outputs may
be connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
The SN54ALS09 is characterized for operation
over the full military temperature range of ?55?C
to 125?C. The SN74ALS09 is characterized for
operation from 0?C to 70?C.
SN74ALS11AD
SN74ALS35AN
The SN74ALS35A contains six independent
noninverters with open-collector outputs. They
perform the Boolean function Y = A. The
open-collector outputs require pullup resistors to
perform correctly. These outputs may be
connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
The SN74ALS35A is characterized for operation
from 0?C to 70?C.
SN74ALS521N
These identity comparators perform comparisons
on two 8-bit binary or BCD words. The
SN74ALS518 provides P = Q outputs, while the
?ALS520 and SN74ALS521 provide P = Q
outputs. The SN74ALS518 has an open-collector
output. The SN74ALS518 and ?ALS520 feature
20-k? pullup resistors on the Q inputs for analog
or switch data.
The SN54ALS520 is characterized for operation
over the full military temperature range of ?55?C
to 125?C. The SN74ALS518, SN74ALS520, and
SN74ALS521 are characterized for operation
from 0?C to 70?C
SN74ALS569AN
The SN74ALS568A decade counter and
?ALS569A binary counters are programmable,
count up or down, and offer both synchronous and
asynchronous clearing. All synchronous functions
are executed on the positive-going edge of the
clock (CLK) input.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR) or
synchronous clear (SCLR). Asynchronous (direct)
clearing overrides all other functions of the device,
while synchronous clearing overrides only the
other synchronous functions. Data is loaded from
the A, B, C, and D inputs by holding load (LOAD)
low during a positive-going clock transition. The
counting function is enabled only when enable P
(ENP) and enable T (ENT) are low and ACLR,
SCLR, and LOAD are high. The up/down (U/D)
input controls the direction of the count. These
counters count up when U/D is high and count
down when U/D is low.
