DS1687-5
? Incorporates Industry-Standard DS1287 PC
Clock plus Enhanced Features Such as Y2K
Compliant
? 3V or 5V Operation
? 64-Bit Silicon Serial Number
? Power-Control Circuitry Supports System
Power-On from Date/Time Alarm or Key
Closure
? 32kHz Output for Power Management
? Crystal-Select Bit Allows RTC to Operate with
6pF or 12.5pF Crystal
? SMI Recovery Stack
? 242 Bytes Battery-Backed NV RAM
? Auxiliary Battery Input
? RAM Clear Input
? Century Register
? Date Alarm Register
? Compatible with Existing BIOS for Original
DS1287 Functions
? Available as Chip (DS1685) or Stand-Alone
Encapsulated DIP (EDIP) with Embedded
Battery and Crystal (DS1687)
? Timekeeping Algorithm Includes Leap-Year
Compensation Valid Through 2099
? Underwriters Laboratory (UL) Recognized
DS17485S-5
The DS17285, DS17485, DS17885, DS17287, DS17487,
and DS17887 real-time clocks (RTCs) are designed to
be successors to the industry-standard DS12885 and
DS12887. The DS17285, DS17485, and DS17885 (hereafter referred to as the DS17x85) provide a real-time
clock/calendar, one time-of-day alarm, three maskable
interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery-backed
NV SRAM. The DS17x85 also incorporates a number
of enhanced functions including a silicon serial number,
power-on/off control circuitry, and 2k, 4k, or 8kbytes of
battery-backed NV SRAM. The DS17287, DS17487, and
DS17887 (hereafter referred to as the DS17x87) integrate
a quartz crystal and lithium energy source into a 24-pin
encapsulated DIP package.
DS1813-10
The DS1813 EconoReset uses a precision
temperature reference and comparator circuit to
monitor the status of the power supply (VCC).
When an out-of-tolerance condition is detected,
an internal power-fail signal is generated which
forces reset to the active state. When VCC returns
to an in-tolerance condition, the reset signal is
kept in the active state for approximately 150ms
to allow the power supply and processor to
stabilize.
The DS1813 also monitors a pushbutton on the
reset output. If the reset line is pulled low, a reset
is generated upon release and will be held in reset
output low for typically 150ms.
DS2181AQ
The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red
Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and
CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when
enabled. The receive side decodes the incoming data and establishes frame, CAS multiframe, and CR
DS2480B
The DS2480B is a serial port to 1-Wire interface chip that supports standard and overdrive speeds. It connects directly to UARTs and 5V RS232 systems. Interfacing to RS232C (?12V levels) requires a passive
clamping circuit and one 5V to ?12V level translator. Internal timers relieve the host of the burden of
generating the time-critical 1-Wire communication waveforms
DS26C31MJ/883Q
DESCRIPTION
The DS26C31 is a quad differential line driver 2? TTL Input Compatible
designed for digital data transmission over balanced
? Outputs Will Not Load Line When VCC = 0V lines. The DS26C31 meets all the requirements of
? Meets the Requirements of EIA Standard RS- EIA standard RS-422 while retaining the low power
422 characteristics of CMOS. The DS26C31 is compatible
with EIA standard RS-422; however, one exception in ? Operation from Single 5V Supply
test methodology is taken. This enables the
? TRI-STATE Outputs for Connection to System construction of serial and terminal interfaces while
Buses maintaining minimal power consumption
DS80C320 ECL
The DS80C320/DS80C323 are pin compatible with all three packages of the standard 80C32 and offer
the same timer/counters, serial port, and I/O ports. In short, the devices are extremely familiar to 8051
users, but provide the speed of a 16-bit processor.
The DS80C320 provides several extras in addition to greater speed. These include a second full hardware
serial port, seven additional interrupts, programmable watchdog timer, power-fail interrupt and reset. The
device also provides dual data pointers (DPTRs) to speed block data memory moves. It can also adjust the
speed of off-chip data memory access to between two and nine machine cycles for flexibility in selecting
memory and peripherals.
