M24128-Drd
M24128-Drd
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M24128-DRDW8TP/K

₹54.00

Features  of M24128-DRD

  • Support for all I2C bus modes– 1 MHz/ 400 kHz/ 100 kHz
  • Memory bank- An EEPROM with 128 Kbits (16 Kbytes)
  • Page Size in Bytes: 64
  • In addition Make a locked page.
  • Wider range of temperatures and voltages—40 to 105 degrees Celsius; 1.7 to 5.5 volts
  • Schmitt trigger inputs are used to filter noise.
  • Cycle time for short writes- Byte Write in 4 milliseconds- Page Write in 4 milliseconds
  • Express cycling stamina. -4,000,000 Write Cycles at 25 °C, – 1,2,000,000 Write cycles at 85 °C & – 900 k Cycles of writing at 105 °C
  • Data storage- at 105 °C for more than 50 years., 200 yr at 55 °C
  • ESD Defense (Human Body Model)– 4000 V
  • Packing is- Halogen-free and RoHS compliant

Characteristics of M24128-DRD

  • SMD/SMT mounting style
  • Case/Package: TSSOP-8
  • Interface types: I2C and 2-Wire
  • Size of Memory: 128 kbit
  • Arrangement: 16 k x 8
  • Minimum Supply Voltage: 1.7 V
  • Maximum Supply Voltage: 5.5 V
  • 40 C for the minimum operating temperature
  • 105 C is the maximum operating temperature.
  • 1 MHz is the maximum clock frequency.
  • Time to Access: 450 ns
  • Retention of Data: 200 Years
  • Maximum Supply Current: 2 mA
  • The M24128-DRD series
  • mandatory requirement: AEC-Q100
  • Packaging: Cut Tape and Reel
  • Maximum Active Read Current: 2 mA
  • STMicroelectronics is a brand.
  • 2 mA is the operating supply current.
  • Voltage Range for Operating Supply: 1.8 to 5.5 V
  • Type of Product: EEPROM

 

6198 in stock

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SKU: CMMIC-0013 Category:
Description

Description of  M24128-DRD

A 128-Kbit serial EEPROM device functioning up to 105 °C is the M24128-DRD. The AEC-Q100 grade 2 reliability standard is adhered to by the it. A straightforward serial I2C compliant interface operating at up to 1MHz is used to access the device. The memory array uses cutting-edge genuine EEPROM (electrically erasable programmable memory) technology.

The M24128-DRD is a byte-alterable memory (16 K 8 bits) that is set up as 256 pages of 64 bytes. It has internal error correction logic, which considerably improves the data integrity. The ST device identity can be obtained from the devices extra Identification Page (64 bytes). Additionally, you may use this page to hold private application parameters that can later be permanently locked in read-only mode.

 

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